- Counting Two-State Transition-Tour Sequences 1 Counting Two-State Transition-Tour Sequences
- Detecting Resistive Shorts for CMOS Domino Circuits Jonathan T.-Y. Chang and Edward J. McCluskey
- Experimental Results for IDDQ and VLV Testing Jonathan T.-Y. Chang*
- Transformed Pseudo-Random Patterns for BIST Nur A. Touba and Edward J. McCluskey
- Orthogonal Scan Paths for Data Path Logic Robert B. Norwood* and Edward J. McCluskey
- A Reliable LZ Data Compressor on Reconfigurable Coprocessors Wei-Je Huang, Nirmal Saxena, and Edward J. McCluskey
- Copyright 2001 by the Center for Reliable Computing, Stanford University. All rights reserved, including the right to reproduce this report, or portions thereof, in any form.
- ELF35 Experiment -Chip and Experiment Design By James C.-M. Li, Jonathan T.-Y. Chang, Chao-Wen Tseng and Edward J. McCluskey
- * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX ALTERING A PSEUDO-RANDOM BIT SEQUENCE
- WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE ? Subhasish Mitra and Edward J. McCluskey
- ANALYSIS OF PATTERN-DEPENDENT AND TIMING-DEPENDENT FAILURES IN AN EXPERIMENTAL TEST CHIP
- SCAN SYNTHESIS FOR ONE-HOT SIGNALS Subhasish Mitra *, LaNae Avra and Edward J. McCluskey
- WORD-VOTER: A NEW VOTER DESIGN FOR TRIPLE MODULAR REDUNDANT Subhasish Mitra and Edward J. McCluskey
- DEPENDABLE ADAPTIVE COMPUTING SYSTEMS THE STANFORD CRC ROAR PROJECT
- Figure 1 2-to-1 Multiplexer. Table 1a Exhaustive Test For Multiplexer.
- A DESIGN DIVERSITY METRIC AND RELIABILITY ANALYSIS FOR REDUNDANT Subhasish Mitra, Nirmal R. Saxena and Edward J. McCluskey
- MINVDD Testing for Weak CMOS ICs Chao-Wen Tseng, Ray Chen, Phil Nigh*, and Edward J. McCluskey
- Copyright 1996 by the Center for Reliable Computing, Stanford University. All rights reserved, including the right to reproduce this report, or portions thereof, in any form.
- ORTHOGONAL SCAN: LOW OVERHEAD SCAN FOR DATA PATHS Robert B. Norwood and Edward J. McCluskey
- OUTPUT ENCODING FOR HAZARD-FREE ROBUST PATH DELAY FAULT TESTABILITY Subhasish Mitra * and Edward J. McCluskey
- IDDQ Data Analysis Using Current Signature James C.M. Li and Edward J. McCluskey
- ACS Implementation of A Robotic Control Algorithm with Fault Tolerant Capabilities
- Figure 1-1 Three Bit Binary Counter. Figure 1-2 Faults in First Flip-Flop of
