- Resistive Bridge Fault Modeling,Simulationand Test Generation Vijay R. Sar-Dessai
- On Comparison of NCR Effectiveness with a Reduced IDDQ Vector Set Sagar Sabade D. M. H. Walker
- Optimal Voltage Testing for Physically-Based Faults Yuyun Liao D.M.H. Walker
- Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification Sagar S. Sabade D. M. H. Walker
- Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction
- CROWNE: Current Ratio Outliers With Neighbor Estimator Sagar S. Sabade D. M. H. Walker
- IDDQ data analysis using neighbor current ratios Sagar S. Sabade, D.M.H. Walker *
- At-Speed Test for Path Delay Faults Using Practical Techniques Wangqi Qiu Jing Wang D. M. H. Walker
- Longest Path Selection for Delay Test Under ProcessVariation* Xiang Lut, Zhuo Lit, Wangqi Qiu', D. M. H. Walkert, Weiping Shi'
- Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis Sagar S. Sabade D. M. H. Walker
- Testing the Path Delay Faults for ISCAS85 Circuit c6288 Wangqi Qiu D. M. H. Walker
- Built-in Current Sensor for IDDQ Test Bin Xue D. M. H. Walker
- Test Generation for Global Delay Faults G. M. Luong and D. M. H. Walker
- Accurate Fault Modeling and Fault Simulation of Resistive Bridges Vijay Sar-Dessai D. M. H. Walker
- Resistive Bridge Fault Modeling, Simulation and Test Generation1 This research was supported by the National Science Foundation under grant MIP-9406946. This research was performed while Vijay
- Abstract--Under manufacturing process variation, a path through a net is called longest if there exists a process condition
- A Circuit Level Fault Model for Resistive Bridges ZHUO LI, XIANG LU, WANGQI QIU, WEIPING SHI and D. M. H. WALKER
- IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop Bin Xue, D. M. H. Walker
- Static Compaction of Delay Tests Considering Power Supply Noise , Xiang Lu*
- Technology Scaling Issues of an IDDQ Built-In Current Sensor Bin Xue, D. M. H. Walker
- Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests Sagar S. Sabade D. M. H. Walker
- Ch ip L e v e l P o w e r S u p p ly P a r titio n in g fo r ID D Q T e stin g U sin g B u ilt-In Cu r r e n t S e n so r s
- Combined Delay Fault Modeling and Simulation Wangqi Qiu*
- Use of Multiple IDDQ Test Metrics for Outlier Identification Sagar S. Sabade D. M. H. Walker
- Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker
- Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation Sagar S. Sabade Duncan M. Walker
- Evaluation of Statistical Outlier Rejection Methods for IDDQ Testing Sagar Sabade Hank Walker
- Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker
- FedEx A Fast Bridging Fault Extractor Zoran Stanojevic
- Defect Localization Using Physical Design and Electrical Test Information
- An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit
- ACM Transcations on Design Automation of Electronic Systems, Vol. 0, No. 0, Oct. 2003, Pages-1-39. 1 IDDX-based Test Methods: A Survey
- Requirements for Practical IDDQ Testing of Deep Submicron Circuits D. M. H. Walker
- FAULT COVERAGE ANALYSIS FOR PHYSICALLY-BASED CMOS BRIDGING FAULTS AT DIFFERENT POWER SUPPLY
- IDDQ Testing of Input Output Resources of SRAM-based FPGAs Lan Zhao D. M. H. Walker Fabrizio Lombardi
- Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
- Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis Zoran Stanojevic
- An EfficientSolution to the Storage CorrespondenceProblem For Large Sequential Circuits
- A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide , Wangqi Qiu
- Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade*
- THE COMPLEX TASK of ensuring the correct operation of ICs becomes more challenging as
- PARADE: PARAmetric Delay Evaluation Under Process Variation* , Wangqi Qiu
- NCR: A Self-scaling, Self-calibrated Metric for IDDQ Outlier Identification Sagar S. Sabade D. M. H. Walker
- A Vector-based Approach for Power Supply Noise Analysis in Test Compaction , Ziding Yue*
- IC Performance Prediction for Test Cost Reduction Jungran Lee
- CodSim A Combined Delay Fault Simulator Wangqi Qiu*
- A Circuit Level Fault Model for Resistive Opens and Bridges , Xiang Lu+
