- L4: AN FPGA-BASED ACCELERATOR FOR DETAILED MAZE ROUTING John A. Nestor, Jeremy Lavine
- 342 IEEE TRANSACTIONS ON EDUCATION, VOL. 51, NO. 3, AUGUST 2008 Experience With the CADAPPLETS Project
- Vitae July 2009 John A. Nestor
- An FPGA-Based Wireless Network Capstone Project John A. Nestor Chris Nadovich
- Experience with the CADAPPLETS Project John A. Nestor
- Nestor 1 P52 FPGA Implementation of a Multilayer Maze Router
- To appear in Proceedings of the International Conference on Microelectronic Systems Education June 1-2, 2003 Integrating Digital, Analog, and Mixed-Signal Design
- Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition Copyright 2003, American Society for Engineering Education
- Web-Based Visualization Tools for Teaching VLSI CAD Algorithms John A. Nestor
- L4 Organization } Key Idea: 2-D Array of Simple PEs
- Session T1A /09/$25.00 2009 IEEE October 18 -21, 2009, San Antonio, TX
- FPGA Implementation of a Maze Routing Accelerator John A. Nestor
- A New Look at Hardware Maze Routing John A. Nestor
- Teaching Computer Organization with HDLs: An Incremental Approach John A. Nestor
- Abstract--This paper describes the development of visualization aids for VLSI Computer-Aided Design
- L3: An FPGA-Based Multilayer Maze Routing Accelerator John A. Nestor
- Vitae July 2011 John A. Nestor
- ECE 491 Fall 2008 Syllabus p 1 of 3 ECE 491 Senior Design I
- To appear in Proceedings International Conference on Microelectronics Systems Education, June 2011 HDL Coding Guidelines for Student Projects
