- Hybrid Slicing: Integrating Dynamic Information with Static Analysis \Lambda
- Hybrid Slicing: Integrating Dynamic Information with Static Analysis
- Support for Symmetric Shadow Memory in Multiprocessors
- Matching Control Flow of Program Versions Vijay Nagarajan, Rajiv Gupta
- UNIVERSITY OF CALIFORNIA Dynamic State Alteration Techniques for Automatically Locating Software Errors
- Extending Path Profiling across Loop Backedges and Procedure Boundaries
- Parallel Processing Letters fl World Scientific Publishing Company
- Value Prediction in VLIW Machines \Lambda Tarun Nakra, Rajiv Gupta and Mary Lou Soffa
- Performance of Multihop Communications Using Logical Topologies on Optical Torus Networks \Lambda
- Capturing the Effects of Code Improving Transformations \Lambda Clara Jaramillo, Rajiv Gupta and Mary Lou Soffa
- Code Compaction of Matching Single-Entry Multiple-Exit Regions ?
- Hiding Program Slices for Software Security Xiangyu Zhang Rajiv Gupta
- Global ContextBased Value Prediction 1 Tarun Nakra, Rajiv Gupta and Mary Lou Soffa
- Distributed Path Reservation Algorithms for Multiplexed All-Optical
- Frequent Value Compression in Data Caches Jun Yang Youtao Zhang Rajiv Gupta
- [to appear: International Conf. on Compiler Construction, Edinburgh, UK, April '94] Reducing the Cost of Data Flow Analysis
- A Fresh Look at Optimizing Array Bound Checking Rajiv Gupta
- Self-Recovery in Server Programs Vijay Nagarajan, Dennis Jeffrey and Rajiv Gupta
- Optimizing Array Bound Checks Using Flow Analysis
- A Representation for Bit Section Based Analysis and Optimization ?
- Path Matching in Compressed Control Flow Traces
- Interprocedural Conditional Branch Elimination y Rastislav Bod'ik Rajiv Gupta Mary Lou Soffa
- Speculative Optimizations for Parallel Programs on Multicores
- Efficient Forward Computation of Dynamic Slices Using Reduced Ordered Binary Decision Diagrams
- Array Data Flow Analysis for LoadStore Optimizations in Superscalar Architectures ?
- Speculative Subword Register Allocation in Embedded Processors
- Enhancing the Performance of 16-bit Code Using Augmenting Instructions
- Copy Or Discard Execution Model For Speculative Parallelization On Multicores Chen Tian Min Feng Vijay Nagarajan Rajiv Gupta
- Refining Data Flow Information using Infeasible Paths ? Rastislav Bod'ik, Rajiv Gupta, and Mary Lou Soffa
- A Code Motion Framework for Global Instruction Scheduling ?
- Load and Store Reuse Using Register File Contents
- Microarchitecture and Compiler Techniques for Dual Width ISA processors
- Data Flow Analysis Driven Dynamic Data Partitioning
- Partial Dead Code Elimination using Slicing Transformations Rastislav Bod'ik Rajiv Gupta
- Load Redundancy Removal through Instruction Reuse junyang@cs.arizona.edu
- Register Pressure Sensitive Redundancy Elimination ? Rajiv Gupta and Rastislav Bod'ik
- Comparison Checking: An Approach to Avoid Debugging of Optimized Code ?
- Compressing Heap Data for Improved Memory Performance Youtao Zhang Rajiv Gupta
- Frequent Value Encoding for Low Power University of California at Riverside
- Supporting Speculative Parallelization in the Presence of Dynamic Data Structures
- Identifying the Root Causes of Memory Bugs Using Corrupted Memory Location Suppression
- Enabling Partial Cache Line Prefetching Through Data Compression
- Integrated Instruction Scheduling and Register Allocation Techniques ?
- This work is supported in part by the National Science Founda-tion, with grants EIA-9971256, EIA-0205286, and CDA-
- Algorithms for Supporting Compiled Communication #
- Performance of Multi--Hop Communications Using Logical Topologies on Optical Torus Networks \Lambda y
- ProfileGuided Java Program Partitioning for Power Aware Computing Sriraman Tallam Rajiv Gupta
- Bit Section Instruction Set Extension of ARM for Embedded Applications
- Path Profile Guided Partial Dead Code Elimination Using Predication \Lambda
- Uni cation of Register Allocation and Instruction Scheduling in Compilers for Fine-Grain Parallel Architectures
- Data Flow Testing Neelam Gupta
- Simple Offset Assignment in Presence of Subword Data Bengu Li Rajiv Gupta
- Effective and Efficient Localization of Multiple Faults Using Value Replacement Dennis Jeffrey
- Synchronization Aware Conflict Resolution for Runtime Monitoring Using Transactional Memory
- Temporal Analysis of Routing Activity for Anomaly Detection in Ad hoc Networks
- Pruning Dynamic Slices With Confidence Xiangyu Zhang Neelam Gupta Rajiv Gupta
- Locating Faults Through Automated Predicate Switching Xiangyu Zhang Neelam Gupta Rajiv Gupta
- Efficient Use of Invisible Registers in Thumb Code Arvind Krishnaswamy Rajiv Gupta
- Locating Faulty Code Using Failure-Inducing Chops Neelam Gupta Haifeng He Xiangyu Zhang Rajiv Gupta
- Extended Whole Program Paths Sriraman Tallam Rajiv Gupta Xiangyu Zhang
- Dynamic Coalescing for 16-Bit Instructions ARVIND KRISHNASWAMY and RAJIV GUPTA
- Selective Backbone Construction for Topology Control in Ad Hoc Networks
- Extending Path Profiling across Loop Backedges and Procedure Boundaries
- COMMUNICATIONS OF THE ACM August 2003/Vol. 46, No. 8 47 pplications written for
- Frequent Value Locality and its Applications JUN YANG and RAJIV GUPTA
- Profile Guided Selection of ARM and Thumb Instructions
- Load-Reuse Analysis: Design and Evaluation Rastislav Bodik Rajiv Gupta Mary Lou Soffa
- Employing Register Channels for the Exploitation of Instruction Level Parallelism
- Compile-time Techniques for Efficient Utilization of Parallel Memories*
- Unified Control Flow and Data Dependence Traces
- A Fine-Grained MIMD Architecture basedupon Register Channels Rajiv Gupta
- The Fuzzy Barrier: A Mechanism for High Speed Synchronization of Processors*
- Dynamic Recognition of Synchronization Operations for Improved Data Race Detection
- A Demand-Driven Analyzer for Data Flow Testing at the Integration Level t
- A Methodology for Controlling the Size of a MARY JEAN HARROLD
- Architectural Support for Shadow Memory in Multiprocessors Vijay Nagarajan and Rajiv Gupta
- ECMon: Exposing Cache Events for Monitoring Vijay Nagarajan Rajiv Gupta
- Dynamic Slicing of Multithreaded Programs for Race Detection Sriraman Tallam
- Avoiding Program Failures Through Safe Execution Perturbations Sriraman Tallam
- The Design and Evaluation of Path Matching Schemes on Compressed Control Flow Traces
- Detecting Virus Mutations Via Dynamic Matching Min Feng Rajiv Gupta
- BugFix: A Learning-Based Tool to Assist Developers in Fixing Bugs Dennis Jeffrey
- ExPert: Dynamic Analysis Based Fault Location via Execution Perturbations Neelam Gupta and Rajiv Gupta
- UNIVERSITY OF CALIFORNIA Speculative Parallelization on Multicore Processors
- UNIVERSITY OF CALIFORNIA IMPRESS: Improving Multicore Performance and Reliability via Efficient Support
- Fault Location via Precise Dynamic Slicing Xiangyu Zhang
- instrumentation instrumented
- SOURCE LEVEL DEBUGGING TECHNIQUES AND TOOLS FOR OPTIMIZED CODE
- Scalable Superscalar Processing Soner Onder
- A DEMAND-DRIVEN APPROACH FOR EFFICIENT INTERPROCEDURAL
- Efficient Register Allocation via Coloring Using Clique Separators
- Experimental Evaluation of Using Dynamic Slices for Fault Location
- Executing Loops on a Fine-Grained MIMD Architecture Sunah Lee Rajiv Gupta 1
- Hybrid Slicing: An Approach for Refining Static Slices Using Dynamic Information \Lambda
- Energy Efficient Frequent Value Data Cache Design Jun Yang (1)
- Does TimeDivision Multiplexing Close the Gap Between Memory and Optical
- An Array Data Flow Analysis based Communication Optimizer ?
- Data Compression Transformations for Dynamically Allocated Data Structures ?
- Pro le Guided Compiler Optimizations Rajiv Gupta
- Optimizing Array Bound Checks Using Flow Analysis 1 Rajiv Gupta
- Compilation Techniques for Parallel Systems Rajiv Gupta
- Dynamic Information Flow Tracking on Multicores Vijay Nagarajan 1
- Register Allocation Via Clique Separators Rajiv Gupta Mary Lou Soffa*
- Ninth International Symposium on High Performance Computer Architecture
- A Shape Matching Approach for Scheduling Fine-Grained Parallelism'
- ResourceSensitive ProfileDirected Data Flow Analysis for Code Optimization \Lambda
- Path Profile Guided Partial Redundancy Elimination Using Speculation \Lambda
- Code Optimization as a Side Effect of Instruction Scheduling \Lambda Rajiv Gupta y
- FV Encoding for Low-Power Data I/O Jun Yang Rajiv Gupta
- Scalability of applications on distributed shared-memory (DSM) multiprocessors is limited by
- Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Li Shang Li-Shiuan Peh Niraj K. Jha
- Cost and Precision Tradeoffs of Dynamic Data Slicing Algorithms
- Fault Localization Using Value Replacement Dennis Jeffrey (1)
- A Framework for Partial Data Flow Analysis* Fbjiv Gupta and Mary Lou Soffa
- ONTRAC: A system for efficient ONline TRACing for debugging Vijay Nagarajan, Dennis Jeffrey, Rajiv Gupta and Neelam Gupta
- Slide 1State_of_state.ppt The State of State: HPCA February 12, 2003 The StateState of StateState
- Whole Execution Traces Xiangyu Zhang Rajiv Gupta
- International Journal o[ Parallel Programming, Vol. 21, No. 3, 1992 Fine-Grained
- CROWNE PLAZA 12021 Harbor Boulevard ANAHEIM-GARDEN GROVE, CA 92840 Toll-Free: 8668888891 Tel: 1-714-8675555
- Cost Effective Dynamic Program Slicing Xiangyu Zhang Rajiv Gupta
- Precise Dynamic Slicing Algorithms Xiangyu Zhang Rajiv Gupta
- SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
- Matching Execution Histories of Program Versions Xiangyu Zhang Rajiv Gupta
- Dynamic Slicing Long Running Programs through Execution Fast Forwarding
- Fault Location and Avoidance in Long-Running MultiThreaded Applications
- Scalable Dynamic Information Flow Tracking and its Applications Rajiv Gupta, Neelam Gupta, Xiangyu Zhang
- A Practical Framework for DemandDriven Interprocedural Data Flow Analysis
- RETROSPECTIVE: Complete Removal of Redundant Expressions
- Enabling Tracing Of Long-Running Multithreaded Programs Via Dynamic Execution Reduction
- Cache replacement algorithms originally developed in the context of simple uniprocessor systems aim to reduce
- Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
- Incorporating Predicate Information Into Branch Predictors Brad Calder
- Compiler Analysis to Support Compiled Communication for HPF--like programs Xin Yuan \Lambda
- A Practical Data Flow Framework for Array Reference Analysis and its Use in Optimizations +
- I E E t IRANSAC710NS O N SOFTWARE ENGINkERING. VOL 16. NO. 1.APRIL IWO 42I Region Scheduling: An Approach for Detecting and
- Distributed path reservation algorithms for multiplexed all--optical interconnection networks \Lambda
- Frequent Value Locality and ValueCentric Data Cache Design
- Distributed Control Protocols For Wavelength Reservation And Their Performance Evaluation 1
- FULLDOC: A Full Reporting Debugger for Optimized Code ?
- Compiler-Assisted Memory Encryption for Embedded Processors
- Bitwidth Aware Global Register Allocation Sriraman Tallam Rajiv Gupta
- Whole Execution Traces and Their Applications
- Dynamic and Compiled Communication in Optical Time{Division{Multiplexed
- Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
- Dynamic Optimization of Micro-Operations Brian Slechta David Crowe Brian Fahs Michael Fertig Gregory Muthler
- SPMD Execution in the Presence of Dynamic Data Structures
- Timestamped Whole Program Path Representation and its Applications
- Caching and Predicting Branch Sequences for Improved Fetch Effectiveness \Lambda
- Towards Locating Execution Omission Errors Xiangyu Zhang
- Learning Universal Probabilistic Models for Fault Localization
- Reconsidering Complex Branch Predictors Daniel A. Jimenez
- Catching Accurate Profiles in Hardware Satish Narayanasamy Timothy Sherwood Suleyman Sair
- Front-End Policies for Improved Issue Efficiency in SMT Processors Ali El-Moursy and David H. Albonesi
- PATH-SENSITIVE, VALUE-FLOW OPTIMIZATIONS OF PROGRAMS Rastislav Bodik
- Runtime Monitoring on Multicores via OASES Vijay Nagarajan and Rajiv Gupta
- This research was sponsored in part by DARPA PAC/C, by Intel Corporation, and by Semiconductor Research Corporation.
- Energy-Ecient Load and Store Reuse Jun Yang Rajiv Gupta
- Variability in Architectural Simulations of Multi-threaded Workloads Alaa R. Alameldeen and David A. Wood
- Mini-threads: Increasing TLP on Small-Scale SMT Processors Joshua Redstone Susan Eggers Henry Levy
- Dynamic Data Dependence Tracking and its Application to Branch Prediction Lei Chen, Steve Dropsho, and David H. Albonesi
- Power-Aware Control Speculation through Selective Throttling Juan L. Aragn1
- Beyond PerformanceBeyond Performance SomeSome otherother challenges for System Designchallenges for System Design
- Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems
- Exploring the VLSI Scalability of Stream Processors Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, and Brian Towles
- Performance Enhancement Techniques for InfiniBandTM Architecture
- Caches and Hash Trees for Efficient Memory Integrity Verification Blaise Gassend, G. Edward Suh, Dwaine Clarke, Marten van Dijk
- Just Say No: Benefits of Early Cache Miss Determination Gokhan Memik
- TCP: Tag Correlating Prefetchers T.J. Watson Research Center
- Inter-cluster Communication Models for Clustered VLIW Processors Andrei Terechko1
- Speculative Parallelization Using State Separation and Multiple Value Prediction
- Enhancing LRU Replacement via Phantom Associativity Min Feng Chen Tian Rajiv Gupta
