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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1 Standby Leakage Power Reduction Technique for
 

Summary: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1
Standby Leakage Power Reduction Technique for
Nanoscale CMOS VLSI Systems
HeungJun Jeon, Yong-Bin Kim, Senior Member, IEEE, and Minsu Choi, Senior Member, IEEE
Abstract--In this paper, a novel low-power design technique
is proposed to minimize the standby leakage power in nanoscale
CMOS very large scale integration (VLSI) systems by generat-
ing the adaptive optimal reverse body-bias voltage. The adap-
tive optimal body-bias voltage is generated from the proposed
leakage monitoring circuit, which compares the subthreshold cur-
rent (ISUB) and the band-to-band tunneling (BTBT) current
(IBTBT). The proposed circuit was simulated in HSPICE using
32-nm bulk CMOS technology and evaluated using ISCAS85
benchmark circuits at different operating temperatures (ranging
from 25
C to 100
C). Analysis of the results shows a maximum of
551 and 1491 times leakage power reduction at 25
C and 100
C,

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering