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Scheduling Instructions with Uncertain Latencies in Asynchronous Architectures

Summary: Scheduling Instructions with Uncertain
Latencies in Asynchronous Architectures
D. K. Arvind and S. Sotelo­Salazar
Department of Computer Science, The University of Edinburgh,
Mayfield Road, Edinburgh EH9 3JZ, Scotland.
Abstract. This paper addresses the problem of scheduling instructions
in micronet­based asynchronous processors (MAP), in which the laten­
cies of the instructions are not precisely known. A PTD scheduler is
proposed which minimises true dependencies, and results are compared
with two list schedulers ­ the Gibbons and Muchnick scheduler, and a
variation of the Balanced scheduler. The PTD scheduler has a lower
time complexity and produces better quality schedules than the other
two when applied to twenty­three loop­ and control­intensive benchmark
1 Introduction
There has been a revival of interest in the use of asynchrony, albeit in a restricted
form known as self­timing, in the design of processor architectures. Asynchron­
ous circuits offer some distinct advantages. Their power consumption is generally
much lower compared to their synchronous equivalent. This is because at any
time only parts of the asynchronous system are active as required, with the rest


Source: Arvind, D. K. - School of Informatics, University of Edinburgh


Collections: Computer Technologies and Information Sciences