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0740-7475/03/$17.00 2003 IEEE Copublished by the IEEE CS and the IEEE CASS NovemberDecember 2003 CONVENTIONAL PIPELINING partitions the combi-

Summary: 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS November­December 2003
CONVENTIONAL PIPELINING partitions the combi-
national logic into smaller chunks and inserts registers at
the boundaries. Wave pipelining takes another approach,
relying on the logic path being long enough and the data
dispersion reasonably small, so the system can send mul-
tiple sets of data (waves) through the logic at a faster
clock rate and without latching the data on the way.
Although wave-pipelined designs enjoy several
advantages over their conventional counterparts, they
require tighter timing constraints because they have no
intermediate registers in which to store intermediate
data. Wave pipelining is especially vulnerable to delay
changes due to variations in process, voltage, and tem-
perature (PVT) and in the operating environment.
Whereas conventional pipelining's performance
depends only on the maximum-delay path, wave
pipelining's performance is also affected by the mini-
mum-delay path. Thus, minimum delay is also a con-
cern for wave-pipelined circuits. Automating


Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University


Collections: Engineering