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A Self-Tuning DVS Processor Using Delay-Error Detection and Correction Shidhartha Das, Sanjay Pant, David Roberts, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Krisztian Flautner*
 

Summary: A Self-Tuning DVS Processor Using Delay-Error Detection and Correction
Shidhartha Das, Sanjay Pant, David Roberts, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Krisztian Flautner*
Department of EECS, University of Michigan, Ann Arbor, MI
*ARM Inc., Cambridge, UK
Abstract
In this paper, we present the implementation and silicon
measurements results of a 64bit processor fabricated in 0.18Ám
technology. The processor employs a delay-error detection and
correction scheme called Razor to eliminate voltage safety margins
and scale voltage 120mV below the first failure point. It achieves
44% energy savings over the worst case operating conditions for a
0.1% targeted error rate at a fixed frequency of 120MHz.
1. Introduction
Recently, we proposed a new voltage management concept for
Dynamic Voltage Scaled (DVS) processors, called Razor [1], along
with initial simulation based results. In this paper we present the
first silicon implementation of a Razor design. We discuss the
circuit structures used in this new implementation and present
silicon measurements for 33 tested dies. The chip implements a
subset of the Alpha instruction set and was fabricated with

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences