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Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
 

Summary: Memory Subsystem Characterization in a 16-Core
Snoop-Based Chip-Multiprocessor Architecture
Francisco J. Villa, Manuel E. Acacio, and José M. García
Departamento de Ingeniería y Tecnología de Computadores,
Universidad de Murcia, 30071 Murcia, Spain
{fj.villa, meacacio, jmgarcia}@ditec.um.es
Abstract. In this paper we present an exhaustive evaluation of the
memory subsystem in a chip-multiprocessor (CMP) architecture com-
posed of 16 cores. The characterization is performed making use of a new
simulator that we have called DCMPSIM and extends the Rice Simula-
tor for ILP Multiprocessors (RSIM) with the functionality required to
model a contemporary CMP in great detail.
To better understand the behavior of the memory subsystem, we pro-
pose a taxonomy of the L1 cache misses found in CMPs which subse-
quently we use to determine where the hot spots of the memory hierarchy
are and, thus, where computer architects have to place special emphasis
to improve the performance of future dense single-chip multiprocessors,
which will integrate 16 or more processor cores.
Keywords: Dense chip-multiprocessors, memory subsystem, snoop-based
cache-coherence, high-performance interconnection networks.

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences