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Summary: 1
Abstract
Fault collapsing is the process of reducing the number
of faults by using redundance and equivalence/dominance
relationships among faults. Exact fault collapsing can be
easily applied locally at the logic gates, however, it is
often ignored for most circuits, due to its high demand of
resources such as execution time and/or memory. In this
paper, we present EGFC, an exact global fault collapsing
tool for combinational circuits. EGFC uses binary deci-
sion diagrams to compute the tests for faults and conse-
quently achieve efficient global fault collapsing.
Experimental results show that EGFC reduces the number
of faults drastically with feasible resources.
Keywords: Global fault collapsing, fault simulation, physi-
cal fault testing.
1 Introduction
To test a digital circuit, an automatic test pattern gener-
ation (ATPG) tool generates a test set that targets possible
physical faults. As the complexity of the digital circuit
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