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Optimal Spare Utilization in Repairable and Reliable Memory Cores , F. Lombardi3
 

Summary: Optimal Spare Utilization in Repairable and Reliable Memory Cores
M. Choi1
, N. Park2
, F. Lombardi3
, Y.B. Kim3
and V. Piuri4
1
Dept of ECE, University of Missouri-Rolla, Rolla, MO 65409-0040, USA
2
Dept of Computer Science, Oklahoma State University, Stillwater, OK 74078-1053, USA
3
Dept of ECE, Northeastern University, Boston, MA 02115, USA
4
Dept of Information Technologies, University of Milan, Bramante 65, 26013 Crema (CR), Italy
Abstract
Advances in System-on-Chip (SoC) technology rely on
manufacturing and assembling high-performance system
cores for many critical applications. Among these cores,
memory occupies the largest portion of the SoC area; this
trend much likely will continue in the future as it is widely

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering