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Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors
 

Summary: Dynamically Managed Multithreaded Reconfigurable
Architectures for Chip Multiprocessors
Matthew A. Watkins
Computer Systems Laboratory
Cornell University, Ithaca, NY
maw72@cornell.edu
David H. Albonesi
Computer Systems Laboratory
Cornell University, Ithaca, NY
albonesi@csl.cornell.edu
ABSTRACT
Prior work has demonstrated that reconfigurable logic can
significantly benefit certain applications. However, recon-
figurable architectures have traditionally suffered from high
area overhead and limited application coverage. We present
a dynamically managed multithreaded reconfigurable archi-
tecture consisting of multiple clusters of shared reconfig-
urable fabrics that greatly reduces the area overhead of re-
configurability while still offering the same power efficiency
and performance benefits. Like other shared SMT and CMP

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University

 

Collections: Computer Technologies and Information Sciences