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Summary: Instruction Scheduling for a Tiled Dataflow Architecture
Martha Mercaldi, Steven Swanson, Andrew Petersen, Andrew Putnam, Andrew Schwerin,
Mark Oskin, Susan J. Eggers
University of Washington
{mercaldi,swanson,petersen,aputnam,schwerin,oskin,eggers}@cs.washington.edu
Abstract
This paper explores hierarchical instruction scheduling for a tiled
processor. Our results show that at the top level of the hierarchy,
a simple profile-driven algorithm effectively minimizes operand
latency. After this schedule has been partitioned into large sections,
the bottom-level algorithm must more carefully analyze program
structure when producing the final schedule.
Our analysis reveals that at this bottom level, good schedul-
ing depends upon carefully balancing instruction contention for
processing elements and operand latency between producer and
consumer instructions. We develop a parameterizable instruction
scheduler that more effectively optimizes this trade-off. We use this
scheduler to determine the contention-latency sweet spot that gen-
erates the best instruction schedule for each application. To avoid
this application-specific tuning, we also determine the parameters
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