Summary: © ECEMA 2000 Concurrent models II 4.1
SECTION 4
CONCURRENT MODELS II
Page
­ Resolved signals 4.3
­ Block statement 4.12
­ Guarded assignment 4.15
­ Guarded target signal assignment 4.21
­ Elaboration and execution of VHDL models 4.35
© ECEMA 2000 Concurrent models II 4.2
Architecture
Block 1
Block 1.1
Block 1.2
Block 2
Entity interface
Ports
Ports
Ports
Ports

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

Collections: Engineering