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Simplified Vector-Thread Architectures for Flexible and Efficient Data-Parallel Accelerators
 

Summary: Simplified Vector-Thread Architectures for
Flexible and Efficient Data-Parallel Accelerators
by
Christopher Francis Batten
B.S. in Electrical Engineering, University of Virginia, May 1999
M.Phil. in Engineering, University of Cambridge, August 2000
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
February 2010
© Massachusetts Institute of Technology 2010. All rights reserved.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
January 29, 2010
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Krste Asanovi´c
Associate Professor, University of California, Berkeley
Thesis Supervisor

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences