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Figure 1. Conventional 6T SRAM cell Figure 2. Proposed 9T SRAM cell

Summary: Figure 1. Conventional 6T SRAM cell
Figure 2. Proposed 9T SRAM cell
A 32nm SRAM Design for Low Power and High
Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi
Department of Electrical and Computer Engineering
Northeastern Univeristy
Boston, MA, USA
Abstract--A SRAM cell must meet stringent requirements
for operation in the sub-micron/nano ranges. A nine
transistor (9T) cell at a 32nm feature size in CMOS is
proposed to accomplish improvements in stability, power
dissipation and performance compared with previous
designs for low-power memory operation. Initially, this
paper presents the optimal transistor sizing for this 9T
SRAM cell considering stability, energy consumption, and
delay. A write bitline balancing scheme is proposed to
reduce the leakage current of the SRAM cell. By optimizing
size and employing the proposed write circuitry scheme, a
saving of 32% in power dissipation is achieved in memory


Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University


Collections: Engineering