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Summary: A G-line-based Network for Fast and Efficient Barrier Synchronization in
Many-Core CMPs
JosŽe L. AbellŽan Juan FernŽandez
Dept. de IngenierŽia y TecnologŽia de Computadores
Facultad de InformŽatica - Universidad de Murcia
30100 Murcia, Spain
{jl.abellan,juanf,meacacio}@ditec.um.es
Manuel E. Acacio
Abstract
Barrier synchronization in shared memory parallel ma-
chines has been widely implemented through busy-waiting
on shared variables. However, typical implementations of
barrier synchronization tend to produce hot-spots in terms
of memory and network contention, thus creating perfor-
mance bottlenecks that become markedly more pronounced
as the number of cores or processors increases. To over-
come such limitations, we present a novel hardware-based
barrier mechanism in the context of many-core CMPs. Our
proposal is based on global interconnection lines (G-lines)
and the S-CSMA technique, which have been recently used
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