Summary: IEEE International Symposium on Circuits and Systems (ISCAS'97), Hong Kong, 912 June 1997, pp. 19401943.
Low Power Multiplication Schemes for Single Multiplier CMOS Based FIR Digital Filter
A.T. Erdogan, T. Arslan and D.H. Horrocks
Cardiff School of Engineering
University of Wales Cardiff, Cardiff CF2 3TF, UK.
Two multiplication schemes are investigated
for the low power implementation of FIR filters
through the reduction of switching activity within
the multiplier section of the filters. The schemes,
which target single multiplier CMOS based DSP
processors, are used with transpose direct form
filter structure and their switching activities are
Power dissipation is becoming a limiting
factor in the realisation of VLSI systems. The