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IEEE International Symposium on Circuits and Systems (ISCAS'97), Hong Kong, 912 June 1997, pp. 19401943. Low Power Multiplication Schemes for Single Multiplier CMOS Based FIR Digital Filter
 

Summary: IEEE International Symposium on Circuits and Systems (ISCAS'97), Hong Kong, 912 June 1997, pp. 19401943.
1
Low Power Multiplication Schemes for Single Multiplier CMOS Based FIR Digital Filter
Implementations
A.T. Erdogan, T. Arslan and D.H. Horrocks
Cardiff School of Engineering
University of Wales Cardiff, Cardiff CF2 3TF, UK.
ARSLAN@cf.ac.uk
ABSTRACT
Two multiplication schemes are investigated
for the low power implementation of FIR filters
through the reduction of switching activity within
the multiplier section of the filters. The schemes,
which target single multiplier CMOS based DSP
processors, are used with transpose direct form
filter structure and their switching activities are
compared.
1. INTRODUCTION
Power dissipation is becoming a limiting
factor in the realisation of VLSI systems. The

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering