Summary: On Combining Formal and Informal Verification
Jun Yuan ? Jian Shen ?? Jacob Abraham ?? Adnan Aziz ??
Abstract. We propose algorithms which combine simulation with sym­
bolic methods for the verification of invariants. The motivation is two­fold.
First, there are designs which are too complex to be formally verified
using symbolic methods; however by the use of symbolic techniques in
conjunction with traditional simulation results in better ``coverage'' rel­
ative to the computational resources used. Additionally, even on designs
which can be symbolically verified, the use of a hybrid methodology of­
ten detects the presence of bugs faster than either formal verification or
simulation.
1 Introduction
In this paper we will be concerned with the problem of design verification; spe­
cifically, the problem of invariant checking over gate­level designs. Traditionally,
designs have been verified by extensive simulation. While offering the benefits of
simplicity and scalability, simulation offers no guarantees of correctness; for large
designs, the fraction of the design space which can be covered in this methodo­
logy becomes vanishingly small. Indeed, there are many examples of designs that
passed extensive simulation, but were still found to contain bugs [4]. This has led
to the proposal of ``formal methods'' for design verification; the adjective formal

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin

Collections: Computer Technologies and Information Sciences