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This paper reports on a new algorithm which carries out combined 3D (4-layer) and over-the-cell (OTC) routing in order to reduce
 

Summary: ABSTRACT
This paper reports on a new algorithm which carries out combined
3D (4-layer) and over-the-cell (OTC) routing in order to reduce
chip area in 3D VLSI technology. In order to cope with the
complexity of the search space, the algorithm is tailored around a
class of heuristic techniques called genetic algorithms. Our results
indicate up to 62% savings in chip area when compared to
conventional multilayer channel routers, using several
internationally well known benchmarks.
1. INTRODUCTION
With silicon VLSI technology approaching its fundamental scaling
limit of 0.2 Ám, the concept of three-dimensional (3D) integration
has been proposed to enhance packing density and speed
performance [1]. Also performance and cost of the widely used
submicron 2D VLSI technology are primarily determined by
interconnection delays and on-chip area. 3D VLSI offers the
possibility of overcoming this problem [1]. Hence being the ideal
technology for complex system-on-chip (SoC) applications. A 3D
VLSI chip consists of a stack of active (silicon) layers made
possible by the silicon on insulator (SOI) technology. In this

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering