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Extending SRT for Parallel Applications in Tiled-CMP Architectures Daniel Sanchez, Juan L. Aragon and Jose M. Garcia

Summary: Extending SRT for Parallel Applications in Tiled-CMP Architectures
Daniel S´anchez, Juan L. Arag´on and Jos´e M. Garc´ia
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia, Spain
Email: {dsanchez, jlaragon, jmgarcia}@ditec.um.es
Reliability has become a first-class consideration issue for
architects along with performance and energy-efficiency. The
increasing scaling technology and subsequent supply voltage
reductions are increasing the susceptibility of architectures
to soft errors. However, mechanisms to achieve full coverage
to errors usually degrade performance in an unacceptable
way for the majority of common users.
Simultaneous and Redundantly Threaded (SRT) [13] is a
fault tolerant architecture in which pairs of threads in a SMT
core redundantly execute the same program instructions. In
this paper, we study the under-explored architectural support
of SRT to reliably execute shared-memory applications. We
show how atomic operations induce a serialization point
between master and slave threads. This bottleneck has an


Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia


Collections: Computer Technologies and Information Sciences