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A NOVEL LOW POWER PIPELINED FFT BASED ON SUBEXPRESSION SHARING FOR WIRELESS LAN APLLICATIONS
 

Summary: A NOVEL LOW POWER PIPELINED FFT BASED ON SUBEXPRESSION SHARING FOR
WIRELESS LAN APLLICATIONS
Wei Han, T. Arslan, A. T. Erdogan and M. Hasan
School of Engineering and Electronics
University of Edinburgh, Edinburgh UK
w.han@ed.ac.uk T.Arslan@ed.ac.uk
ABSTRACT
This paper proposes a novel low power multiplier-less
radix-4 Single-path Delay Commutator (R4SDC) FFT
processor architecture for wireless LAN (IEEE 802.11
standard) applications, where short FFTs are utilised in
the implementation of the physical layer. The multiplier-
less architecture uses shift and addition operations to
realize complex multiplications. By combining a new
commutator architecture, and low power butterfly
architectures with this approach, the resulting power
savings are around 19% and 35% for 64-point and 16-
point radix-4 FFTs respectively, as compared to a
conventional FFT architecture based on non-Booth coded
Wallace tree multiplier.

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering