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A Novel Pre-Truncated Fixed-Width Digital Squarer Ashkan Ashrafi and Sudheep Thota
 

Summary: A Novel Pre-Truncated Fixed-Width Digital Squarer
Ashkan Ashrafi and Sudheep Thota
Department of Electrical and Computer Engineering
San Diego State University
5500 Campanile Dr., San Diego, CA 92182, USA
Abstract-- This paper presents a novel architecture for a
fixed-width pre-truncated squarer. In this architecture, the
input of the squarer is partially truncated. The rest of the
truncation is occurred at the partial product array. The pre-
truncation reduces the actual wordlength of the squarer and
consequently reduces the complexity of its partial-product
array but, it increases the arithmetic error. The partial-product
array of the squarer is modified to mitigate this error. The
statistical errors of the proposed squarer are calculated and
compared with other designs. The squarer is implemented using
TSMC 0.13m technology. The post synthesis data of the
implementation is provided in this paper, which shows a
significant reduction in the chip area.
I. INTRODUCTION
ixed-width digital squarers are useful arithmetic blocks in

  

Source: Ashrafi, Ashkan - Department of Electrical and Computer Engineering, San Diego State University

 

Collections: Engineering; Computer Technologies and Information Sciences