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ARCHITECTURE AND DESIGN METHODOLOGY FOR SYNTHESIZABLE RECONFIGURABLE ARRAY TARGETING
 

Summary: ARCHITECTURE AND DESIGN METHODOLOGY FOR
SYNTHESIZABLE RECONFIGURABLE ARRAY TARGETING
WIRELESS SYSTEM-ON-CHIP APPLICATIONS
Cheng Zhan", Sami Khawaml, Tughrul Arslan1'2, lain Lindsay'
School of Electronics and Engineering University of Edinburgh, Edinburgh, EH9 3JL, UK
2
Institute for System Level Integration, Alba Campus Livingston, EH54 7EG, UK
(c.zhan, Sami.Khawam, Tughrul.Arslan, 1ain.LindsayJ@ed.ac.uk
ABSTRACT
This paper presents a novel domain specific
reconfigurable architecture and an associate
design methodology for System-on-Chip (SoC)
plafform which provides flexibility as well as low-
power consumption. Two Viterbi decoders, which
are widely used in wireless communication system,
are implemented on the proposed architecture
using the proposed design methodology. The
measured performance shows that our architecture
is a perfect compromise between the ASICs and
generic FPGAs, and hence suitable for future

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering