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Summary: A Low Overhead Fault Tolerant Coherence Protocol
for CMP Architectures
Ricardo Fern´andez-Pascual, Jos´e M. Garc´ia,
Manuel E. Acacio
Dpto. Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia
SPAIN
{r.fernandez,jmgarcia,meacacio}@ditec.um.es
Jos´e Duato
Dpto. Inform´atica de Sistemas y Computadores
Universidad Polit´ecnica de Valencia
SPAIN
jduato@disca.upv.es
Abstract
It is widely accepted that transient failures will appear
more frequently in chips designed in the near future due to
several factors such as the increased integration scale. On
the other hand, chip-multiprocessors (CMP) that integrate
several processor cores in a single chip are nowadays the
best alternative to more efficient use of the increasing num-
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