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Reducing Instruction Cache Energy Using Gated Wordlines Mukaya Panich
 

Summary: Reducing Instruction Cache Energy Using Gated Wordlines
by
Mukaya Panich
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degree of
Master of Engineering in Electrical Engineering and Computer Science
at the Massachusetts Institute of Technology
August 20, 1999
Copyright 1999 Mukaya Panich. All rights reserved.
The author hereby grants to M.I.T. permission to reproduce and
distribute publicly paper and electronic copies of this thesis
and to grant others the right to do so.
Author________________________________________________________________________
Department of Electrical Engineering and Computer Science
August 20, 1999
Certified by ____________________________________________________________________
Professor Krste Asanovic
Thesis Supervisor
Accepted by ___________________________________________________________________
Professor Arthur C. Smith

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences