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Summary: MUTATION-BASED VALIDATION OF HIGH-LEVEL
MICROPROCESSOR IMPLEMENTATIONS
Jorge Campos and Hussain Al-Asaad
Department of Electrical and Computer Engineering
University of California, Davis, CA
E-mail: {jcampos, halasaad} @ece.ucdavis.edu
Abstract
In this paper we present a preliminary method of
validating a high-level microprocessor implementation
by generating a test sequence for a collection of ab-
stract design error models that can be used to compare
the responses of the implementation against the speci-
fication. We first introduce a general description of the
abstract mutation-based design error models that can
be tailored to span any coverage measure for micro-
processor validation. Then we present the clustering-
and-partitioning technique that single-handedly makes
the concurrent design error simulation of a large set of
design errors efficient and allows for the acquisition of
statistical data on the distribution of design errors
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