Summary: ¡£¢¥¤ ¦§¢¥¤ ¨© ¢ !¨"© # ©§#$%'& (£¢©
$)¡0&13245 !©©¥ ¨"©687!9
A. C. McCormick, P. M. Grant, J. S. Thompson, T. Arslan and A. T. Erdogan
Dept. Electronics & Electrical Engineering, The University of Edinburgh
The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, U.K.
The power consumption of multi-carrier CDMA receivers implemented in di-
gital hardware is considered. A low power block based architecture is invest-
igated for the combiner sub-system, and compared with a multiply accumulate
circuit approach. Simulations using data consistent with typical performance
of a multi-carrier CDMA receiver indicate that the block based approach can
produce a power reduction of around 50%.
Multi-Carrier CDMA (code division multiple access) [1, 2] is a spread spectrum
technology which combines the advantages of OFDM (orthogonal frequency division
multiplexing) and CDMA to produce a spectrally efficient multi-user radio access sys-
tem which may be applied in future mobile wireless systems beyond the 3rd generation.
In such systems, the power consumption of a mobile receiver may be a significant is-
sue. A multi-carrier CDMA receiver contains two main system blocks, an FFT block
to demodulate the OFDM signals and a combiner block which equalises the signal and
separates out the coded users. The combiner can employ a variety of techniques such