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Summary: Coordinated Power Management of Periodic Real-Time Tasks
on Chip Multiprocessors
Vinay Devadas Hakan Aydin
Department of Computer Science
George Mason University
Fairfax, VA 22030
{vdevadas, aydin}@cs.gmu.edu
Abstract--In this paper, we undertake the problem of
minimizing system-level energy on chip-multicore processors
(CMPs) executing a periodic real-time workload. Our frame-
work has two components: i.) a static phase that selects a subset
of cores upon which the workload can be executed without
dissipating excessive static power and performs task-to-core
allocation, ii.) a dynamic phase that involves managing the
selected cores at run-time through coordinated power manage-
ment framework that exploits Dynamic Voltage and Frequency
Scaling (DVFS) as well as multiple idle states offered by
modern CMP architectures, to reduce the dynamic power. We
explicitly consider the unique traits of the currently available
CMP architectures that distinguish them from multiprocessors,
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