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A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors
 

Summary: A Two-Level Directory Architecture for
Highly Scalable cc-NUMA Multiprocessors
Manuel E. Acacio, Jose┤ Gonza┤lez, Member, IEEE Computer Society,
Jose┤ M. Garci┤a, Member, IEEE, and Jose┤ Duato, Member, IEEE
Abstract--One important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra
memory required to store the directory information. It is desirable that the directory memory overhead be kept as low as possible, and
that it scales very slowly with the size of the machine. Unfortunately, current directory architectures provide scalability at the expense
of performance. This work presents a scalable directory architecture that significantly reduces the size of the directory for large-scale
configurations of a multiprocessor without degrading performance. First, we propose multilayer clustering as an effective approach to
reduce the width of directory entries. Based on this concept, we derive three new compressed sharing codes, some of them with a
space complexity of O log2 log2 N­ Ů­ Ů­ Ů for an N-node system. Then, we present a novel two-level directory architecture to eliminate the
penalty caused by compressed directories in general. The proposed organization consists of a small full-map first-level directory (which
provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides in-
excess information for all the lines). The proposals are evaluated based on extensive execution-driven simulations (using RSIM) of a
64-node cc-NUMA multiprocessor. Results demonstrate that a system with a two-level directory architecture achieves the same
performance as a multiprocessor with a big and nonscalable full-map directory, with a very significant reduction of the memory
overhead.
Index Terms--Scalability, directory memory overhead, two-level directory architecture, compressed sharing codes, unnecessary
coherence messages, cc-NUMA multiprocessor.
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Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences