Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
An FPGA Host-Multithreaded Functional Model for SPARC v8 Zhangxi Tan
 

Summary: 1
An FPGA Host-Multithreaded Functional Model for SPARC v8
Zhangxi Tan
Computer Science Division
UC Berkeley, USA
xtan@cs.berkeley.edu
Krste Asanovic
Computer Science Division
UC Berkeley, USA
krste@cs.berkeley.edu
David Patterson
Computer Science Division
UC Berkeley, USA
pattersn@cs.berkeley.edu
1. Introduction
The RAMP project [1] aims to create a FPGA based hardware
emulator for future manycore systems, which will scale to 1000
processor cores on several multi-FPGA boards, such as BEE3 board
[2]. At the same time, the emulated processor cores can support
running real life workload (e.g OS and unmodified application

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences