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Thesis Overview: Reducing Branch Misprediction Penalty through Confidence Estimation
 

Summary: Thesis Overview:
Reducing Branch Misprediction Penalty through Confidence Estimation
Juan Luis Aragón
Universidad de Murcia (SPAIN),
Dept. Ingeniería y Tecnología de Computadores
Advisors: José González and Antonio González
February 25, 2003
jlaragon@ditec.um.es
Control dependences are one of the major limitations to increase the performance of current processors. A branch instruction
supposes an interruption of the sequential flow of instructions traversing the pipeline because the next instruction address is
unknown until the branch is executed. However, the fetch stage should introduce the successor instruction following the
branch as soon as possible in order to maximize processor performance. Control speculation is employed in order to achieve
this goal, predicting the outcome of the branch, guessing the successor address and speculatively starting the execution of
those instructions from the predicted path. But despite the important benefits provided by branch prediction schemes, there
are many mispredicted branches. This means that the pipeline is filled with many wrong path instructions, being necessary
flushing the pipeline and restoring the correct state of the processor.
The delay between the time the branch misprediction is discovered and the processor starts fetching the correct path is known
as branch misprediction penalty. This penalty results in performance degradation and also in an increase in energy
consumption, since many useless instructions are processed and executed. Furthermore, many current processors have
designs targeted at very high clock frequencies which leads to longer pipelines (e.g. more than 20 stages in the Intel Pentium

  

Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences