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Memory-Side Prefetching for Linked Data Structures Christopher J. Hughes and Sarita Adve
 

Summary: Memory-Side Prefetching for Linked Data Structures
Christopher J. Hughes and Sarita Adve
Department of Computer Science
University of Illinois at Urbana-Champaign
Urbana, IL 61801-2987
cjhughes,sadve @cs.uiuc.edu
UIUC CS Technical Report UIUCDCS-R-2001-2221, May 2001
Abstract
This work studies a memory-side prefetching technique to hide latency incurred by inherently serial
accesses to linked data structures (LDS). A programmable prefetch engine sits close to memory and traverses
LDS independently from the processor. The prefetch engine can run ahead of the processor because of its
low latency, high bandwidth path to memory. This allows the prefetch engine to initiate data transfers earlier
than the processor and pipeline multiple such transfers over the network.
We evaluate the proposed memory-side prefetching scheme for the pointer-intensive Olden benchmark
suite, comparing both to a system without any prefetching and one with a state-of-the-art processor-side
software prefetching scheme for LDS. For the six benchmarks where LDS memory stall time is significant,
the memory-side scheme reduces execution time by an average of 27% (range of 0% to 62%) compared
to a system without any prefetching. Compared to processor-side prefetching, the memory-side scheme
reduces execution time in the range of 20% to 50% for three of the six applications, is about the same for
two applications, and is worse by 18% for one application. We conclude that memory-side prefetching

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences