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An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors
 

Summary: 1
An Evaluation of Speculative Instruction Execution
on Simultaneous Multithreaded Processors
Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers and Henry M. Levy
University of Washington
Abstract
Modern superscalar processors rely heavily on speculative execution for performance. For
example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for
SPECINT95 are speculative. Without speculation, processor resources on such machines would
be largely idle. In contrast to superscalars, simultaneous multithreaded (SMT) processors achieve
high resource utilization by issuing instructions from multiple threads every cycle. An SMT pro-
cessor thus has two means of hiding latency: speculation and multithreaded execution. However,
these two techniques may conflict; on an SMT processor, wrong-path speculative instructions
from one thread may compete with and displace useful instructions from another thread. For this
reason, it is important to understand the trade-offs between these two latency-hiding techniques,
and to ask whether multithreaded processors should speculate differently than conventional super-
scalars.
This paper evaluates the behavior of instruction speculation on SMT processors using both
multiprogrammed (SPECINT and SPECFP) and multithreaded (the Apache Web server) work-
loads. We measure and analyze the impact of speculation and demonstrate how speculation on an

  

Source: Anderson, Richard - Department of Computer Science and Engineering, University of Washington at Seattle

 

Collections: Computer Technologies and Information Sciences