Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
A Novel 32-bit Scalable Multiplier Architecture Yeshwant Kolla
 

Summary: A Novel 32-bit Scalable Multiplier Architecture
Yeshwant Kolla
SUN Microsystems, Inc
Burlington, MA, 01803, USA
Yeshwant.Kolla@sun.com
Yong-Bin Kim
Dept. opf ECE, Northeastern
University
Boston, MA, 02115, USA
ybk@ece.neu.edu
John Carter
School of
Computing,University of Utah
Salt Lake City, UT,USA
retrac@cs.utah.edu
ABSTRACT
In this paper, we present a novel hybrid multiplier archi-
tecture that has the regularity of linear array multipliers
and the performance of tree multipliers and is highly scal-
able to higher-order multiplication. This multiplier topol-

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering