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Summary: A High Performance, Energy Efficient GALS Processor Microarchitecture with
Reduced Implementation Complexity £
YongKang Zhu , David H. Albonesi Ý
and Alper Buyuktosunoglu Þ
Department of Electrical and Computer Engineering, University of Rochester
Computer Systems Laboratory, Cornell University Ý
IBM T. J. Watson Research Center Þ
Abstract
As the costs and challenges of global clock distribution
grow with each new microprocessor generation, a Globally
Asynchronous, Locally Synchronous (GALS) approach be-
comes an attractive alternative. One proposed GALS ap-
proach, called a Multiple Clock Domain (MCD) processor,
achieves impressive energy savings for a relatively low per-
formance cost. However, the approach requires separat-
ing the processor into four domains, including separating
the integer and memory domains which complicates load
scheduling, and the implementation of 32 voltage and fre-
quency levels in each domain. In addition, the hardware-
based control algorithm, though effective overall, produces
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