| | |
Summary: A Novel Approach to Reduce L2 Miss Latency in Shared-Memory
Multiprocessors
Manuel E. Acacio, Jos´e Gonz´alez, Jos´e M. Garc´ia
Dpto. Ing. y Tecnolog´ia de Computadores
Universidad de Murcia
30071 Murcia (Spain)
meacacio,joseg,jmgarciaˇ @ditec.um.es
Jos´e Duato
Dpto. Inf. de Sistemas y Computadores
Universidad Polit´ecnica de Valencia
46071 Valencia (Spain)
jduato@gap.upv.es
Abstract
Recent technology improvements allow multiprocessor
designers to put some key components inside the processor
chip, such as the memory controller, the coherence hard-
ware and the network interface/router. In this work we ex-
ploit such integration scale, presenting a novel node archi-
tecture aimed at reducing the long L2 miss latencies and
|
