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128 IEEE Transactionson Consumer Electronics,Vol. 49, No. 1,FEBRUARY 2003 A Novel Coefficient Ordering based Low Power Pipelined Radix-4
 

Summary: 128 IEEE Transactionson Consumer Electronics,Vol. 49, No. 1,FEBRUARY 2003
A Novel Coefficient Ordering based Low Power Pipelined Radix-4
FFT Processor for Wireless LAN Applications
M. Hasan, T. Arslan and J.S. Thompson
Abstract - The FFT processor is a critical block in all
multi-carrier systems used primarily in the mobile
environment. The portability requirement of these systems is
mainly responsible for the need of low power FFT
architectures. This paper proposes a technique to reduce the
power consumption of a popular lowpower radix-4 pipelined
FFT processor by modi&ing its operation sequence. The
complex multiplier is one of the mostpower consuming blocks
in the FFT processor. The switching activity at its fixed
coeflcient input can be drastically reduced by coefficient
ordering and hence its power consumption. Coefficient
ordering requires a novel commutator architecture which can
handle the corresponding data sequencing as per new
coefficient ordering. The resulting power saving is around
23% and 9%for the 16-point and 64-point radix-4 pipelined
FFT processor respectively. This approach is very attractive

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering