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Appears in the Proceedings of the 3rd International Symposium on Networks-on-Chip (NOCS-3), May 2009 Silicon-Photonic Clos Networks for Global On-Chip Communication
 

Summary: Appears in the Proceedings of the 3rd International Symposium on Networks-on-Chip (NOCS-3), May 2009
Silicon-Photonic Clos Networks for Global On-Chip Communication
Ajay Joshi*, Christopher Batten*, Yong-Jin Kwon, Scott Beamer, Imran Shamim*
Krste Asanovi┤c, Vladimir Stojanovi┤c*
* Department of EECS, Massachusetts Institute of Technology, Cambridge, MA
Department of EECS, University of California, Berkeley, CA
Abstract
Future manycore processors will require energy-
efficient, high-throughput on-chip networks. Silicon-
photonics is a promising new interconnect technology
which offers lower power, higher bandwidth density, and
shorter latencies than electrical interconnects. In this pa-
per we explore using photonics to implement low-diameter
non-blocking crossbar and Clos networks. We use analyti-
cal modeling to show that a 64-tile photonic Clos network
consumes significantly less optical power, thermal tuning
power, and area compared to global photonic crossbars
over a range of photonic device parameters. Compared
to various electrical on-chip networks, our simulation re-
sults indicate that a photonic Clos network can provide

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences