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To appear in Proceedings of HPCA3 (February, 1997) The Impact of InstructionLevel Parallelism on
 

Summary: To appear in Proceedings of HPCA­3 (February, 1997)
The Impact of Instruction­Level Parallelism on
Multiprocessor Performance and Simulation Methodology
Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve
Department of Electrical and Computer Engineering
Rice University
Houston, Texas 77005
fvijaypai---parthas---saritag@rice.edu
Abstract
Current microprocessors exploit high levels of
instruction­level parallelism (ILP) through techniques
such as multiple issue, dynamic scheduling, and non­
blocking reads. This paper presents the first detailed
analysis of the impact of such processors on shared­
memory multiprocessors using a detailed execution­
driven simulator. Using this analysis, we also exam­
ine the validity of common direct­execution simulation
techniques that employ previous­generation processor
models to approximate ILP­based multiprocessors.
We find that ILP techniques substantially reduce

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences