Exact global fault collapsing can be easily applied locally
at the logic gates, however, it is often ignored for large cir-
cuits due to its high demand of execution time and/or
memory. In this paper, we present AGFC, an approximate
global fault collapsing tool for combinational circuits.
Experimental results show that (i) AGFC reduces the num-
ber of faults drastically with feasible resources and (ii)
AGFC produces significantly better results than existing
Global fault collapsing, fault simulation, physical fault
testing, combinational circuits.
To test a digital circuit, an automatic test pattern genera-
tion (ATPG) tool generates a test set that targets possible
physical faults. As the complexity of the digital circuit
increases, the possible number of physical faults increases
that consequently leads to a significant slow down of the