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Array Data Layout for the Reduction of Cache Conflicts Naraig Manjikian and Tarek S. Abdelrahman
 

Summary: Array Data Layout for the Reduction of Cache Conflicts
Naraig Manjikian and Tarek S. Abdelrahman
Department of Electrical and Computer Engineering
The University of Toronto
Toronto, Ontario, Canada M5S 1A4
email: {nmanjiki,tsa}@eecg.toronto.edu
Abstract--The performance of applications on large-
scale shared-memory multiprocessors depends to a large ex-
tent on cache behavior. Cache conflicts among array ele-
ments in loop nests degrade performance and reduce the ef-
fectiveness of locality-enhancing optimizations. In this pa-
per, we describe a new technique for reducing cache conflict
misses. The technique, called cache partitioning, logically
divides cache capacity into equal parts, and allocates arrays
in memory such that each array maps into a separate parti-
tion in the cache. We present experimental results from KSR
and SGI machines to demonstrate the effectiveness of cache
partitioning in eliminating cache conflicts and in realizing
the full benefit of locality-enhancing techniques for both se-
quential and parallel execution.

  

Source: Abdelrahman, Tarek S. - Department of Electrical and Computer Engineering, University of Toronto

 

Collections: Computer Technologies and Information Sciences