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Global Multi-Threaded Instruction Scheduling: Technique and Initial Results
 

Summary: Global Multi-Threaded Instruction Scheduling:
Technique and Initial Results
Guilherme Ottoni David I. August
Department of Computer Science
Princeton University
{ottoni, august}@princeton.edu
Recently, the microprocessor industry has reached hard
physical and micro-architectural limits that have prevented
the continuous clock-rate increase, which had been the ma-
jor source of performance gains for decades. These im-
pediments, in conjunction with the still increasing transis-
tor counts per chip, have driven all major microprocessor
manufacturers toward Chip Multiprocessor (CMP) designs.
Although CMPs are able to concurrently pursue multiple
threads of execution, they do not directly improve the per-
formance of most applications, which are written in sequen-
tial languages. In effect, the move to CMPs has shifted even
more the task of improving performance from the hard-
ware to the software. In order to support more effective
parallelization of sequential applications, computer archi-

  

Source: August, David - Department of Computer Science, Princeton University

 

Collections: Computer Technologies and Information Sciences