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A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
 

Summary: A 1GHz Direct Digital Frequency Synthesizer
Based on the Quasi-Linear Interpolation Method
Ashkan Ashrafi, Aleksandar Milenkovi, and Reza Adhami
Department of Electrical and Computer Engineering
The University of Alabama in Huntsville
Huntsville, AL 35899, USA
Abstract--The paper presents a novel architecture for a direct
digital frequency synthesizer (DDFS) based on the Quasi-
Linear interpolation (QLIP) method. The four-segment QLIP
is utilized to realize a DDFS with a spurious free dynamic
range (SFDR) of 63.2dBc. The DDFS chip featuring a 5-stage
pipeline is implemented in TSMC 0.13m technology. The chip
occupies 9874m2
, consumes 8.2W/MHz, and runs at 1GHz
clock rate.
I. INTRODUCTION
irect digital frequency synthesizers (DDFS) play a very
important role in modern digital communication
systems. They are essential parts in Spread Spectrums such
as Bluetooth devices and Radars due to their high speed

  

Source: Ashrafi, Ashkan - Department of Electrical and Computer Engineering, San Diego State University
Milenkovi, Aleksandar - Department of Electrical and Computer Engineering, University of Alabama in Huntsville

 

Collections: Computer Technologies and Information Sciences; Engineering