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Accurate Macro-modeling for Leakage Current for IDDQ Test Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
 

Summary: 1
Accurate Macro-modeling for Leakage Current for IDDQ Test
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
, Nohpill Park
Department of Electrical and Computer Engineering
Northeastern University, Boston, MA USA,
Department of Electrical and Computer Engineering
University of Missouri-Rolla, Rolla, MO USA
,
Department of Computer Science
Oklahoma State University, Stillwater, OK USA
.
E-mail: kkkim@ece.neu.edu, ybk@ece.neu.edu, choim@umr.edu
, npark@cs.okstate.edu
Indexing terms: Leakage Current, Subthreshold Leakage Current, Gate Tunneling Leakage Current, IDDQ,
Test Pattern Generator.
Extended abstract: Due to the continued scaling of technology and supply and threshold voltage,
leakage power has become more and more significant in the power supply dissipation of nanoscale
CMOS circuits. Therefore, testing deep sub-micron (DSM) chips with millions of transistors is a difficult
challenge.

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering