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Assessing Merged DRAM/Logic Technology Submitted to Integration, the VLSI Journal
 

Summary: Assessing Merged DRAM/Logic Technology
Submitted to Integration, the VLSI Journal
Yong-Bin Kim*(Contact person) Tom W. Chen**
*Department of Electrical Engineering
University of Utah
50 South Central Campus Drive
Salt Lake City, UT 84112
Tel (801) 581-4445 Fax (801) 581-5281
Email: ybk@ee.utah.edu
**Department of Electrical and Computer Engineering
Colorado State University
Fort Collins, CO 80523
Tel: 970-491-6574 Fax: 970-491-2249
Email: chen@engr.colostate.edu.
November 11, 1998
Abstract
This paper describes the impact of DRAM process on the logic circuit performance of Memory/Logic
Merged Integrated Circuit and the alternative circuit design technologyto o set the performancepenalty.
Extensive circuit and routing simulations have been performed to study the logic circuit performance
degradation when the merged chip is implemented on DRAM process. Three logic processes(0.5 m,

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering