Evaluating the Yield of Repairable SRAMs for
Marco Ottavi, Member, IEEE, Luca Schiano, Student Member, IEEE, Xiaopeng Wang Member, IEEE,
Yong-Bin Kim, Senior Member, IEEE, Fred J. Meyer, Member, IEEE, and Fabrizio Lombardi, Senior
An accurate yield evaluation is essential for selecting redundancy allocation and testing strategies for memories.
Yield evaluation can resolve the many issues revolving around cost-effective BIST and ATE-based solutions for higher
test transparency. In this paper, two yield calculation methodologies for SRAM arrays are proposed. General yield
expressions for VLSI chips are initially presented. The regular and repetitive structure of a SRAM array is exploited
and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield evaluation
methods for one dimensional redundant memory arrays are introduced and compared for Automatic Test Equipment
(ATE) application. The first method is based on the sum of probabilities of all repairable fault patterns; the second
method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE
usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are
Manufacturing, SRAM, Yield, Markov modeling, ATE, Redundancy.