Summary: Implementing Pfairness on a Symmetric Multiprocessor #
Philip Holman and James H. Anderson
Department of Computer Science
University of North Carolina
Chapel Hill, NC 27599­3175
E­mail: {holman,anderson}@cs.unc.edu January 2004
Abstract
We consider the implementation of a Pfair scheduler on a symmetric multiprocessor (SMP). Although
SMPs are in many ways well­suited for Pfair scheduling, experimental results presented herein suggest that
bus contention resulting from the simultaneous scheduling of all processors can substantially degrade perfor­
mance. To correct this problem, we propose a staggered model for Pfair scheduling that strives to improve
performance by more evenly distributing bus tra#c over time. Additional simulations and experiments with
a scheduler prototype are presented to demonstrate the e#ectiveness of the staggering approach. In addition,
we discuss other techniques for improving performance while maintaining worst­case predictability. Finally,
we present an e#cient scheduling algorithm to support the proposed model and briefly explain how existing
Pfair results apply to staggered scheduling.
# Work supported by NSF grants CCR 9988327, ITR 0082866, CCR 0204312, and CCR 0309825, and by a grant of software
provided by the QNX corporation.

1 Introduction

Source: Anderson, James - Department of Computer Science, University of North Carolina at Chapel Hill

Collections: Computer Technologies and Information Sciences