Summary: T0: A Single­Chip Vector Microprocessor
with Reconfigurable Pipelines
Krste Asanovi'c, James Beck, Bertrand Irissou,
Brian E. D. Kingsbury, & John Wawrzynek
Department of Electrical Engineering
and Computer Sciences
University of California at Berkeley
Berkeley, CA 94720­1776
and the
International Computer Science Institute
1947 Center Street, Suite 600
Berkeley, CA 94704­1105
Abstract
A single­chip fixed­point vector microprocessor is described. The chip contains
a MIPS­II RISC core with a 1 KB instruction cache, dual eight­way parallel
vector arithmetic pipelines, a 128­bit memory interface, and an 8­bit serial host
interface. Each vector arithmetic pipeline contains a cascade of six functional
units that can be dynamically reconfigured by each instruction. The resulting
peak performance is 4.3 billion 32­bit arithmetic operations per second at a
clock speed of 45 MHz.

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

Collections: Computer Technologies and Information Sciences