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Architectural trade-offs in the design of low power FIR filtering cores
 

Summary: Architectural trade-offs in the design of low power
FIR filtering cores
A.T. Erdogan, E. Zwyssig and T. Arslan
Abstract: There is a continuous drive for methodologies and approaches of low power design. This
is mainly driven by the surge in portable computing. On the other hand, the design of low power
systems for different portable applications is not a simple task. This is because of the number of
constraints that influence the power consumption of a device. In addition to issues of performance
and functionality, there is a need to satisfy strict test coverage constraints. The authors investigate
the impact of DSP architectural realisation, multiplier type, and the choice of number
representation on the overall power consumption of DSP devices. Work in the literature so far
has concentrated on the effect of these on a part or a section of a DSP system. Furthermore the
effect of DfT circuits on the overall performance is studied. A hearing aid device is considered as an
example of a system with strict power/area constraints. It is shown that the choice of multiplier
architecture and number representation should be carefully considered when specific DSP
architectural choices are made. The results are demonstrated with a number of specially designed
DSP architectures for the implementation of FIR filtering algorithms on hearing aid devices.
1 Introduction
FIR filtering algorithms such as subband decomposition,
noise reduction and echo cancellation are executed
repetitively in DSP systems such as hearing aids. Therefore

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering